Seamless FPGA (разработчик: Mentor Graphics) — With the Mentor Graphics Seamless CVE, systems-designers and software developers incorporating Xilinx FPGAs based on the Platform FPGA initiative now can validate the fluid hardware/software interfaces in a virtual prototype while both the hardware and software designs are still in progress. The process will help preserve the time-to-market advantage of FPGAs by ensuring early insight into design problems and at the same time enable the hardware and software design flexibility inherent in FPGAs and processors. For Xilinx target customers in time-constrained markets, such as communication systems design and wireless telephony infrastructure, maintaining tight design cycles is often the difference between product success and failure.
``As our new generation of Platform FPGA devices achieve widespread adoption as true-ASIC replacements, Mentor's Seamless CVE will be a key design flow tool for ensuring that our customers maintain the time-to-market benefits that are characteristic of FPGAs, while at the same time exploiting the new capabilities of a fluid hardware/software boundary to achieve the ultimate in system performance and functionality, said Rich Sevcik, senior vice president of IP, support and software at Xilinx. ``Mentor Graphics is recognized as being at the forefront of co-verification technology in the ASIC space and its technology is easily modified for the large-FPGA space given our devices' similarity to existing system-on-chip architectures.