SystemSI (разработчик: Sigrity) — SystemSI addresses the challenges associated with high speed designs with comprehensive chip-to-chip signal integrity analysis solutions. SystemSI is available in two configurations. SystemSI - Parallel Bus Analysis targets source synchronous designs. SystemSI - Serial Link Analysis focuses on projects with SerDes channels. SystemSI includes a block based schematic editor to make it easy to get started with very basic data. As design work progresses, models are swapped in to reflect the detail of design structures. SystemSI includes frequency domain, time domain and statistical analysis methods to ensure robust parallel bus and serial link interface implementations.